The demand for small size, large capacity nonvolatile semiconductor memory devices is increasing at a significant rate and a NAND type flash memory which can realize high integration and large capacity is being focused on. However, in order to realize such small size devices there is a need to further increase miniaturization of wiring patterns for example, even though a reduction in design rules is becoming more and more difficult. In recent years, a large number of nonvolatile semiconductor memory devices in which memory cells are arranged three dimensionally in order to increase the integration of memory have been proposed.
However, the memory cells which are arranged three dimensionally in a conventional nonvolatile semiconductor memory device are electrically insulated from the semiconductor substrate. Also, both a channel and a drain of a select gate which is formed in/on both ends of a memory cell which is stacked in a conventional semiconductor memory device in which the memory cells are arranged three dimensionally are formed by the same conductive select gate transistor. A control electrode is not connected to the channel region of this select gate transistor.
Due the structure outlined above, carriers accumulate in the channel region of a memory cell or select gate transistor, the threshold level of the channel region shifts and problems such as unstable operations may occur.